1. Field of the Invention
The present invention relates to a semiconductor device including an electrostatic protective element (input/output protective element, and also, hereinafter simply referred to as a protective element) for preventing electrostatic damage of a semiconductor element, and a method of manufacturing the same.
2. Description of the Related Art
As a method for preventing the electrostatic damage of a semiconductor element, there is a method in which protective elements as shown in FIG. 1 are provided, using diodes at respective input/output terminals. The protective elements are equivalent to the diodes provided in parallel to gate electrodes of transistors (semiconductor elements) connected to the input/output terminals. In FIG. 1, the breakdown voltage of the diode is set lower than a gate breakdown voltage, so that a breakdown current applied from the input/output terminal is made to flow to the diode and is made not to be applied to the gate electrode, and the semiconductor element is protected.
Hereinafter, a conventional manufacturing process of a semiconductor device including a general protective element will be described with reference to FIGS. 7A to 7C and FIGS. 8A to 8C.
(1) A P well 2 in which a P-type impurity such as boron is introduced and an N well 3 in which an N-type impurity such as phosphorus is introduced are formed in a semiconductor substrate 1. Thereafter, element separation is made by SiO2 films 4 having a thickness of about 0.4 xcexcm (FIG. 7A).
Three element regions are shown in the drawing, which are xe2x80x9ca region A in which a protective element (diode) is formedxe2x80x9d, xe2x80x9ca region B in which an Nch transistor is formedxe2x80x9d, and xe2x80x9ca region C in which a Pch transistor is formedxe2x80x9d from the left.
(2) A gate oxide film 5 having a thickness of about 0.005 to 0.02 xcexcm is formed on the semiconductor substrate 1. Thereafter, a conductive film which becomes gate electrodes is deposited to a thickness of about 0.2 xcexcm, and a photolithography and etching step is carried out to form gate electrodes 6 (FIG. 7B). As the conductive film which becomes the gate electrodes, there is a polysilicon film in which an impurity is introduced at a high concentration, a polycide film or the like.
(3) Next, a photolithography step is carried out so that the region C where the Pch transistor is formed is covered with a resist 7.
Thereafter, an N-type impurity such as phosphorus is implanted by an ion implantation method at an implantation energy of 30 to 50 keV and at an implantation amount of 3 to 5 E 13 atoms/cm2 so that Nxe2x88x92type impurity layers 8 are formed (FIG. 7C).
(4) Next, a photolithography step is carried out so that the region B where the Nch transistor is formed and the region A where the protective element is formed are covered with a resist 9. Thereafter, a P-type impurity such as boron or boron difluoride is implanted by the ion implantation method at an implantation energy of 30 to 50 keV and an implantation amount of 3 to 5 E 13 atoms/cm2 so that Pxe2x88x92type impurity layers 10 are formed (FIG. 8A).
(5) Next, after a SiO2 film having a thickness of about 0.2 to 0.3 xcexcm is deposited, etch-back is carried out by an RIE method to form a side wall 11. Thereafter, a photolithography step is carried out so that the region C where the Pch transistor is formed is covered with a resist 12. Next, an N-type impurity such as arsenic or phosphorus is implanted by the ion implantation method at an implantation energy of 30 to 50 keV and an implantation amount of 2 to 3 E 15 atoms/cm2 so that N+-type impurity layers 13 are formed (FIG. 8B).
(6) Next, a photolithography step is carried out so that the region B where the Nch transistor is formed and the region A where the protective element is formed are covered with a resist 14. Thereafter, a P-type impurity such as boron or boron difluoride is implanted by the ion implantation method at an implantation energy of 30 to 50 keV and an implantation amount of 2 to 3 E 15 atoms/cm2 so that P+-type impurity layers 15 are formed (FIG. 8C).
(7) Thereafter, an anneal treatment is carried out at 800xc2x0 C. for 30 to 60 minutes so that the implanted impurities are activated, and the protective element and the respective transistors are formed.
As a semiconductor device is microminiaturized, a gate oxide film also becomes thin. That is, since a gate breakdown voltage also becomes low, it becomes necessary that the breakdown voltage of a diode used as a protective element is also set low.
Like this, as a method for strengthening electrostatic damage resistance by setting the breakdown voltage of a diode low, there is a method disclosed in Japanese Unexamined Patent Publication No. HEI 6(1994)-349852 or No. HEI 7(1995)-111267.
Japanese Unexamined Patent Publication No. HEI 6(1994)-349852 discloses a method in which an impurity is introduced into a well of a portion used as a protective element at a high concentration before formation of a gate electrode to decrease the breakdown voltage.
Japanese Unexamined Patent Publication No. HEI 7(1995)-111267 discloses a method in which the breakdown voltage is reduced by newly adding an N++ region, and the degree of a drop is adjusted by the distance between the N++ region and an N+ region.
However, in such usual manufacturing methods, in order to reduce the breakdown voltage of a diode, it is necessary to newly add at least three steps of xe2x80x9ca photolithography step of specifying a portion where an impurity is introduced at a high concentrationxe2x80x9d, xe2x80x9can introduction step of introducing the impurity at the high concentrationxe2x80x9d, and xe2x80x9ca step of removing a resistxe2x80x9d. Besides, it becomes necessary to provide one photomask for specifying the region where the impurity is introduced at the high concentration. Thus, there are problems that the manufacturing costs are raised and the manufacturing period is prolonged.
Besides, in Japanese Unexamined Patent Publication No. HEI 7(1995)-111267, since the breakdown voltage is determined by the distance between the N++ region and the N+ region, it is necessary to control this distance with high precision. Thus, there is a problem that the precision of superposition of an exposure apparatus is required to be higher than normal precision.
In view of the above, the present invention has a purpose to provide a semiconductor device including a protective element having a low breakdown voltage without adding a new step and a photomask, and a method of manufacturing the same.
According to the present invention, provide is a semiconductor device comprising an electrostatic protective element of the semiconductor device including a first conductivity type substrate and a second conductivity type high concentration diffusion layer formed on a surface of the substrate, and a semiconductor element including a source/drain and a gate electrode, wherein a first conductivity type diffusion layer having a higher concentration than the first conductivity type substrate is provided in an entire region under the second conductivity type high concentration diffusion layer.
Further, according to the present invention, provided is a method of manufacturing the above-mentioned semiconductor device comprising: introducing an impurity into a region for forming the electrostatic protective element after the gate electrode is formed on the first conductivity type substrate to form the second conductivity type high concentration diffusion layer and the first conductivity type diffusion layer.
According to the present invention, after the gate electrode is formed on the substrate, impurities introduced to mainly form the source/drain are also implanted at the same time into the protective element region for preventing electrostatic damage, so that the impurity concentration of the protective element region can be made high.
Besides, according to the present invention, since the impurity concentration of the region of the electrostatic damage protective element is made high, the breakdown voltage can be reduced without adding a new step, and as a result, electrostatic damage resistance can be improved.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.